Using a Field Programmable Gate Array
for MRFM cantilever control

Jon Jacky, University of Washington, Seattle

with Matt Ettus (Ettus Research, Inc.), Joe Garbini, Tom Kriewall, John Sidles (UW)

MRFM cantilever control


Goal: Avoid custom hardware, minimize custom programming, code we produce should be re-usable by ourselves and others.

Why control the cantilever?

For us, control means damping. The controller is a filter.

Cantilever has large Q for big excursions and narrow bandwidth.

BUT imaging experiments demand that we reduce Q.

This can be done without reducing SNR.


Heterodyne control

Motivation: all of the information is within a few hundred Hz of cantilever resonant frequency.

Technique: "mix down" input signal to near DC, by multipling with reference frequency near resonance.

Advantages:


Technology experiences

Commercial "software radio" products (VME boards, RTOS). Emulated heterodyne control at RF -- BUT

GNU Radio


GNU Radio technology stack

Integrated design from volts to GUI.

Each layer depends on the one below, well-defined interface to each.

Each layer could be substituted (different technology, but same interface).

Developers are encouraged to program several layers (optimize across the whole stack).


GNU Radio hardware

Universal Sofware Radio Peripheral (USRP)


FPGA programming

FPGA: sea of logic gates and flipflops, your program connects them.

Design your own special-purpose computer (DSP or ...)


Limitations of our FPGA program

FPGA is almost full!

Limitations: latency, also 16-bit integer signal and filter coefficients.

Latency is about 12 -- 14 samples, at mixed-down sampling period:
about 400 usec at 31.25 kHz sampling frequency, 50 usec at 250 kHz.

Maybe heterodyne control not such a good idea for acoustic cantilever after all.
To get acceptable latency, sampling frequency is much greater than reference frequency!

Try it anyway!


Filter characteristics I

Sampling frequency 31.5 kHz, appreciable phase shift caused by 400 usec latency.


Filter characteristics II

Sampling frequency 250 kHz, little phase shift caused by 50 usec latency, but notice error in amplitude.


Revising the FPGA program

Experiments planned:

We can have several (many) FPGA programs that make different tradeoffs. Could select a different one for each voxel.

For this, we need to program the FPGA ourselves.


GNU Radio development

Process optimized for rich functionality, high performance, rapid progress and distribution

For example:


http://usrp.svnrepository.com/usrp/trac.cgi/browser/trunk/fpga/toplevel/mrfm/mrfm_proc.v